chipflow.sim.build
==================

.. py:module:: chipflow.sim.build

.. autoapi-nested-parse::

   Build CXXRTL shared libraries from HDL sources.

   This module provides functions to compile Amaranth, Verilog, and SystemVerilog
   designs into CXXRTL shared libraries for fast simulation.



Functions
---------

.. autoapisummary::

   chipflow.sim.build.build_cxxrtl
   chipflow.sim.build.build_cxxrtl_from_amaranth


Module Contents
---------------

.. py:function:: build_cxxrtl(sources, top_module, output_dir, output_name = None, include_dirs = None, defines = None, optimization = '-O2', debug_info = True)

   Build a CXXRTL shared library from HDL sources.

   :param sources: List of Verilog/SystemVerilog source files
   :param top_module: Name of the top-level module
   :param output_dir: Directory for build artifacts
   :param output_name: Name for output library (default: top_module)
   :param include_dirs: Additional include directories for Verilog
   :param defines: Verilog preprocessor defines
   :param optimization: C++ optimization level (default: -O2)
   :param debug_info: Include CXXRTL debug info (default: True)

   :returns: Path to the compiled shared library


.. py:function:: build_cxxrtl_from_amaranth(elaboratable, top_module, output_dir, amaranth_platform=None, extra_sources = None, **kwargs)

   Build CXXRTL from an Amaranth Elaboratable.

   This function generates Verilog from an Amaranth design and compiles it
   to a CXXRTL shared library, optionally combining with extra Verilog/SV sources.

   :param elaboratable: Amaranth Elaboratable to simulate
   :param top_module: Name for the top module
   :param output_dir: Directory for build artifacts
   :param amaranth_platform: Amaranth platform (optional)
   :param extra_sources: Additional Verilog/SV files to include
   :param \*\*kwargs: Additional arguments passed to build_cxxrtl()

   :returns: Path to the compiled shared library