chipflow_lib.steps
==================

.. py:module:: chipflow_lib.steps

.. autoapi-nested-parse::

   Steps provide an extensible way to modify the `chipflow` command behavior for a given design



Classes
-------

.. autoapisummary::

   chipflow_lib.steps.IOSignature
   chipflow_lib.steps.StepBase


Package Contents
----------------

.. py:class:: IOSignature(direction, width = 1, invert = False, all_have_oe = False, init=None)

   Bases: :py:obj:`amaranth.lib.wiring.Signature`


   An :py:obj:`Amaranth Signature <amaranth.lib.wiring.Signature>` used to decorate wires that would usually be brought out onto a port on the package.
   This class is generally not directly used.
   Instead, you would typically utilize the more specific
   :py:obj:`InputIOSignature`, :py:obj:`OutputIOSignature`, or :py:obj:`BidirIOSignature` for defining pin interfaces.

   :param direction: Input, Output or Bidir
   :param width: width of port, default is 1
   :param invert: Polarity inversion. If the value is a simple :class:`bool`, it specifies inversion for
        the entire port. If the value is an iterable of :class:`bool`, the iterable must have the
        same length as the width of :py:`io`, and the inversion is specified for individual wires.
   :param all_have_oe: controls whether each output wire is associated with an individual Output Enable bit
        or a single OE bit will be used for entire port, the default value is False, indicating that a
        single OE bit controls the entire port.
   :param init: a  :ref:`const-castable object <lang-constcasting>` for the initial values of the port


   .. py:property:: direction
      :type: amaranth.lib.io.Direction


      The direction of the IO port


   .. py:method:: width()

      The width of the IO port, in wires



   .. py:method:: invert()

      A tuple as wide as the IO port, with a bool for the polarity inversion for each wire



   .. py:method:: options()

      Options set on the io port at construction

      Valid options are:
          "all_have_oe": For a bidirectional port, each wire can
          have it's direction dynamically controlled seperately,
          so each wire also has a corresponding Output Enable wire.
          "init": the initial value that this io port will have at power-up and reset.



   .. py:method:: annotations(*args)

      Annotate an interface object.

      Subclasses of :class:`Signature` may override this method to provide annotations for
      a corresponding interface object. The default implementation provides none.

      See :mod:`amaranth.lib.meta` for details.

      :returns: :py:`tuple()`
      :rtype: iterable of :class:`~.meta.Annotation`



.. py:class:: StepBase(config={})

   Bases: :py:obj:`abc.ABC`


   Helper class that provides a standard way to create an ABC using
   inheritance.


   .. py:method:: build_cli_parser(parser)

      Build the cli parser for this step



   .. py:method:: run_cli(args)

      Called when this step's is used from `chipflow` command