chipflow_lib.platforms

This module defines the functionality you use in you code to target the ChipFlow platform

Classes

IOSignature

An Amaranth Signature used to decorate wires that would usually be brought out onto a port on the package.

Functions

OutputIOSignature(width, **kwargs)

This creates an Amaranth Signature which is then used to decorate package output signals

InputIOSignature(width, **kwargs)

This creates an Amaranth Signature which is then used to decorate package input signals

BidirIOSignature(width, **kwargs)

This creates an Amaranth Signature which is then used to decorate package bi-directional signals

Package Contents

class chipflow_lib.platforms.IOSignature(direction, width=1, invert=False, all_have_oe=False, init=None)

Bases: amaranth.lib.wiring.Signature

An Amaranth Signature used to decorate wires that would usually be brought out onto a port on the package. This class is generally not directly used. Instead, you would typically utilize the more specific InputIOSignature, OutputIOSignature, or BidirIOSignature for defining pin interfaces.

Parameters:

  • direction (amaranth.lib.io.Direction) – Input, Output or Bidir

  • width (int) – width of port, default is 1

  • invert (Union[bool, collections.abc.Iterable[bool]]) – Polarity inversion. If the value is a simple bool, it specifies inversion for the entire port. If the value is an iterable of bool, the iterable must have the same length as the width of io, and the inversion is specified for individual wires.

  • all_have_oe (bool) – controls whether each output wire is associated with an individual Output Enable bit or a single OE bit will be used for entire port, the default value is False, indicating that a single OE bit controls the entire port.

  • init – a const-castable object for the initial values of the port

property direction: amaranth.lib.io.Direction

The direction of the IO port

Return type:

amaranth.lib.io.Direction

width()

The width of the IO port, in wires

Return type:

int

invert()

A tuple as wide as the IO port, with a bool for the polarity inversion for each wire

Return type:

int

options()

Options set on the io port at construction

Valid options are:

“all_have_oe”: For a bidirectional port, each wire can have it’s direction dynamically controlled seperately, so each wire also has a corresponding Output Enable wire. “init”: the initial value that this io port will have at power-up and reset.

Return type:

dict

annotations(*args)

Annotate an interface object.

Subclasses of Signature may override this method to provide annotations for a corresponding interface object. The default implementation provides none.

See amaranth.lib.meta for details.

Returns:

tuple()

Return type:

iterable of Annotation

chipflow_lib.platforms.OutputIOSignature(width, **kwargs)

This creates an Amaranth Signature which is then used to decorate package output signals intended for connection to the physical pads of the integrated circuit package.

Parameters:

  • width (int) – specifies the number of individual output wires within this port, each of which will correspond to a separate physical pad on the integrated circuit package.

  • init – a const-castable object for the initial values of the port

chipflow_lib.platforms.InputIOSignature(width, **kwargs)

This creates an Amaranth Signature which is then used to decorate package input signals intended for connection to the physical pads of the integrated circuit package.

Parameters:

  • width (int) – specifies the number of individual input wires within this port, each of which will correspond to a separate physical pad on the integrated circuit package.

  • init – a const-castable object for the initial values of the port

chipflow_lib.platforms.BidirIOSignature(width, **kwargs)

This creates an Amaranth Signature which is then used to decorate package bi-directional signals intended for connection to the physical pads of the integrated circuit package.

Parameters:

  • width (int) – specifies the number of individual input/output wires within this port. Each pair of input/output wires will correspond to a separate physical pad on the integrated circuit package.

  • all_have_oe (bool, optional) – controls whether each output wire is associated with an individual Output Enable bit or a single OE bit will be used for entire port, the default value is False, indicating that a single OE bit controls the entire port.

  • init – a const-castable object for the initial values of the port