chipflow_lib.platforms

This module defines the functionality you use in you code to target the ChipFlow platform

Classes

SiliconPlatformPort	Represents an abstract library I/O port that can be passed to a buffer.
IOSignature	An Amaranth Signature used to decorate wires that would usually be brought out onto a port on the package.
IOModel	Options for IO Ports
Process	IC manufacturing process
GAPackageDef	Definiton of a grid array package, with pins or pads in a regular array of 'width' by 'height' pins
QuadPackageDef	Definiton of a package a row of 'width* pins on the top and bottom of the package and 'height' pins
BareDiePackageDef	Definition of a package with pins on four sides, labelled north, south, east, west
JTAGPins	Pins for a JTAG interface
PowerPins	A matched pair of power pins, with optional notation of the voltage range

Functions

OutputIOSignature(width, **kwargs)	This creates an Amaranth Signature which is then used to decorate package output signals
InputIOSignature(width, **kwargs)	This creates an Amaranth Signature which is then used to decorate package input signals
BidirIOSignature(width, **kwargs)	This creates an Amaranth Signature which is then used to decorate package bi-directional signals

Package Contents

class chipflow_lib.platforms.SiliconPlatformPort(component, name, port, *, invert=False)

Bases: amaranth.lib.io.PortLike

Represents an abstract library I/O port that can be passed to a buffer.

The port types supported by most platforms are SingleEndedPort and DifferentialPort. Platforms may define additional port types where appropriate.

Note

amaranth.hdl.IOPort is not an instance of amaranth.lib.io.PortLike.

Parameters:

• component (str)

• name (str)

• port (chipflow_lib.platforms._utils.Port)

• invert (bool)

property direction

Direction of the port.

Return type:

Direction

class chipflow_lib.platforms.IOSignature(**kwargs)

Bases: amaranth.lib.wiring.Signature

An Amaranth Signature used to decorate wires that would usually be brought out onto a port on the package. This class is generally not directly used. Instead, you would typically utilize the more specific InputIOSignature, OutputIOSignature, or BidirIOSignature for defining pin interfaces.

Parameters:

kwargs (typing_extensions.Unpack[IOModel])

property direction: amaranth.lib.io.Direction

The direction of the IO port

Return type:

amaranth.lib.io.Direction

property width: int

The width of the IO port, in wires

Return type:

int

property invert: collections.abc.Iterable[bool]

A tuple as wide as the IO port, with a bool for the polarity inversion for each wire

Return type:

collections.abc.Iterable[bool]

property options: IOModelOptions

Options set on the io port at construction

Return type:

IOModelOptions

annotations(*args)

Annotate an interface object.

Subclasses of Signature may override this method to provide annotations for a corresponding interface object. The default implementation provides none.

See amaranth.lib.meta for details.

Returns:

tuple()

Return type:

iterable of Annotation

class chipflow_lib.platforms.IOModel

Bases: IOModelOptions

Options for IO Ports

Attributes:

• direction – io.Direction.Input, io.Direction.Output or io.Direction.Bidir

• width – width of port, default is 1

• all_have_oe – controls whether each output wire is associated with an individual Output Enable bit or a single OE bit will be used for entire port, the default value is False, indicating that a single OE bit controls the entire port.

• invert – Polarity inversion. If the value is a simple bool, it specifies inversion for the entire port. If the value is an iterable of bool, the iterable must have the same length as the width of io, and the inversion is specified for individual wires.

• allocate_power – Whether a io power domain should be set on this interface. NB there is only one of these, so IO with multiple IO power domains must be split up.

• interface_power_domains – the name of the available power domains on the interface

• clock_domain – the name of the Amaranth.ClockDomain for this port. NB there is only one of these, so IO with multiple input clocks must be split up.

• init – a Const value for the initial values of the port

chipflow_lib.platforms.OutputIOSignature(width, **kwargs)

This creates an Amaranth Signature which is then used to decorate package output signals intended for connection to the physical pads of the integrated circuit package.

Parameters:

• width (int) – specifies the number of individual output wires within this port, each of which will correspond to a separate physical pad on the integrated circuit package.

• kwargs (typing_extensions.Unpack[IOModelOptions])

chipflow_lib.platforms.InputIOSignature(width, **kwargs)

This creates an Amaranth Signature which is then used to decorate package input signals intended for connection to the physical pads of the integrated circuit package.

Parameters:

• width (int) – specifies the number of individual input wires within this port, each of which will correspond to a separate physical pad on the integrated circuit package.

• kwargs (typing_extensions.Unpack[IOModelOptions])

chipflow_lib.platforms.BidirIOSignature(width, **kwargs)

This creates an Amaranth Signature which is then used to decorate package bi-directional signals intended for connection to the physical pads of the integrated circuit package.

Parameters:

• width (int) – specifies the number of individual input/output wires within this port. Each pair of input/output wires will correspond to a separate physical pad on the integrated circuit package.

• kwargs (typing_extensions.Unpack[IOModelOptions])

class chipflow_lib.platforms.Process(*args, **kwds)

Bases: enum.Enum

IC manufacturing process

class chipflow_lib.platforms.GAPackageDef(/, **data)

Bases: BasePackageDef

Definiton of a grid array package, with pins or pads in a regular array of ‘width’ by ‘height’ pins on the left and right

The pins are identified by a 2-tuple of row and column, counting from the bottom left hand corner when looking at the underside of the package. Rows are identfied by letter (A-Z), and columns are identified by number.

The grid may be complete (i.e. width * height pins) or there may be pins/pads missing (Often a square in the middle of the package (AKA P, but this model doesn’t require this). The missing pins from the grid are identified either by the missing_pins field or the perimeter field

Attributes:

• width – The number of pins across on the top and bottom edges

• hieght – The number of pins high on the left and right edges

• layout_type (GALayoutType) – Pin layout type

• channel_width – For GALayoutType.PERIMETER, GALayoutType.CHANNEL, GALayoutType.ISLAND the number of initial rows before a gap

• island_width – for GALayoutType.ISLAND, the width and height of the inner island

• missing_pins – Used for more exotic types instead of channel_width & island_width. Can be used in conjection with the above.

• additional_pins – Adds pins on top of any of the configuration above

Parameters:

data (Any)

This includes the following types of package: .. csv-table: :header: Package, Description CPGA, Ceramic Pin Grid Array OPGA, Organic Pin Grid Array SPGA, Staggared Pin Grid Array CABGA: chip array ball grid array CBGA and PBGA denote the ceramic or plastic substrate material to which the array is attached. CTBGA, thin chip array ball grid array CVBGA, very thin chip array ball grid array DSBGA, die-size ball grid array FBGA, fine ball grid array / fine pitch ball grid array (JEDEC-Standard[9]) or FCmBGA, flip chip molded ball grid array LBGA, low-profile ball grid array LFBGA, low-profile fine-pitch ball grid array MBGA, micro ball grid array MCM-PBGA, multi-chip module plastic ball grid array nFBGA, New Fine Ball Grid Array PBGA, plastic ball grid array SuperBGA (SBGA), super ball grid array TABGA, tape array BGA TBGA, thin BGA TEPBGA, thermally enhanced plastic ball grid array TFBGA or thin and fine ball grid array UFBGA and UBGA and ultra fine ball grid array based on pitch ball grid array. VFBGA, very fine pitch ball grid array WFBGA, very very thin profile fine pitch ball grid array wWLB, Embedded wafer level ball grid array

model_post_init(__context)

Override this method to perform additional initialization after __init__ and model_construct. This is useful if you want to do some validation that requires the entire model to be initialized.

property bringup_pins: BringupPins

To aid bringup, these are always in the same place for each package type. Should include core power, clock and reset.

Power, clocks and resets needed for non-core are allocated with the port.

Return type:

BringupPins

class chipflow_lib.platforms.QuadPackageDef(/, **data)

Bases: BasePackageDef

Definiton of a package a row of ‘width* pins on the top and bottom of the package and ‘height’ pins on the left and right

The pins are numbered anti-clockwise from the top left hand pin.

This includes the following types of package: .. csv-table: :header: “Package”, “Description” “QFN”, “quad flat no-leads package. It’s assumed the bottom pad is connected to substrate.” “BQFP”, “bumpered quad flat package” “BQFPH”, “bumpered quad flat package with heat spreader” “CQFP”, “ceramic quad flat package” “EQFP”, “plastic enhanced quad flat package” “FQFP”, “fine pitch quad flat package” “LQFP”, “low profile quad flat package” “MQFP”, “metric quad flat package” “NQFP”, “near chip-scale quad flat package.” “SQFP”, “small quad flat package” “TQFP”, “thin quad flat package” “VQFP”, “very small quad flat package” “VTQFP”, “very thin quad flat package” “TDFN”, “thin dual flat no-lead package.” “CERQUAD”, “low-cost CQFP”

Attributes:

• width – The number of pins across on the top and bottom edges

• hight – The number of pins high on the left and right edges

Parameters:

data (Any)

model_post_init(__context)

Override this method to perform additional initialization after __init__ and model_construct. This is useful if you want to do some validation that requires the entire model to be initialized.

property bringup_pins: BringupPins

To aid bringup, these are always in the same place for each package type. Should include core power, clock and reset.

Power, clocks and resets needed for non-core are allocated with the port.

Return type:

BringupPins

class chipflow_lib.platforms.BareDiePackageDef(/, **data)

Bases: BasePackageDef

Definition of a package with pins on four sides, labelled north, south, east, west with an integer identifier within each side, indicating pads across or down from top-left corner

Attributes:

• width (int) – Number of die pads on top and bottom sides

• height (int) – Number of die pads on left and right sides

Parameters:

data (Any)

model_post_init(__context)

Override this method to perform additional initialization after __init__ and model_construct. This is useful if you want to do some validation that requires the entire model to be initialized.

property bringup_pins: BringupPins

To aid bringup, these are always in the same place for each package type. Should include core power, clock and reset.

Power, clocks and resets needed for non-core are allocated with the port.

Return type:

BringupPins

class chipflow_lib.platforms.JTAGPins

Pins for a JTAG interface

class chipflow_lib.platforms.PowerPins

A matched pair of power pins, with optional notation of the voltage range