Intro to chipflow.toml

Intro to chipflow.toml#

The chipflow.toml file provides configuration for your design with the ChipFlow platform.

Let’s start with a typical example:

[chipflow]
project_name = "test-chip"

[chipflow.top]
soc = "my_design.design:MySoC"

[chipflow.steps]
silicon = "chipflow_lib.steps.silicon:SiliconStep"

[chipflow.clocks]
default = 'sys_clk'

[chipflow.resets]
default = 'sys_rst_n'

[chipflow.silicon]
process = "gf130bcd"
package = "pga144"

[chipflow.silicon.pads]
# System
sys_clk   = { type = "clock", loc = "114" }
sys_rst_n = { type = "reset", loc = "115" }

[chipflow.silicon.power]
dvss0        = { type = "power", loc =   "1" }
dvdd0        = { type = "ground", loc =   "9" }
vss0         = { type = "power", loc =  "17" }
vdd0         = { type = "ground", loc =  "25" }
dvss1        = { type = "power", loc =  "33" }
dvdd1        = { type = "ground", loc =  "41" }
vss1         = { type = "power", loc =  "49" }
vdd1         = { type = "ground", loc =  "57" }
dvss2        = { type = "power", loc =  "65" }
dvdd2        = { type = "ground", loc =  "73" }
vss2         = { type = "power", loc =  "81" }
vdd2         = { type = "ground", loc =  "89" }
dvss3        = { type = "power", loc =  "97" }
dvdd3        = { type = "ground", loc = "105" }
vss3         = { type = "power", loc = "113" }
vdd3         = { type = "ground", loc = "121" }
dvss4        = { type = "power", loc = "129" }
dvdd4        = { type = "ground", loc = "137" }

[chipflow]#

[chipflow]
project_name = "my_project"

The project_name is a human-readable identifier for this project. If not set, the tool and library will use the project name configured in pyproject.toml.

[chipflow.steps]#

The steps section allows overriding or addition to the standard steps available from chipflow_lib.

For example, if you want to override the standard silicon preparation step, you could derive from chipflow_lib.steps.silicon.SiliconStep, add your custom functionality and add the following to your chipflow.toml, with the appropriate Python qualified name :

[chipflow.stepe]
silicon = "my_design.steps.silicon:SiliconStep"

You probably won’t need to change these if you’re starting from an example repository.

[chipflow.clocks]#

[chipflow.silicon]#

[chipflow.silicon]
process = "ihp_sg13g2"
package = "pga144"

The silicon section sets the Foundry process (i.e. PDK) that we are targeting for manufacturing, and the physical package we want to place our design inside. You’ll choose the process and package based in the requirements of your design.

Available processes#

Process
Supported
pad rings
Notes

sky130

caravel

Skywater 130nm

gf180

caravel

GlobalFoundries 180nm

gf130bcd

pga144

GlobalFoundries 130nm BCD

ihp_sg13g2

pga144

IHP SG13G2 130nm SiGe

Available pad rings#

Pad ring

Pad count

Pad locations

Notes
cf20
20
N1 … N7
S1 … S7
E1 … E3
W1 … W3
Bare die package with 20 pins

pga144

144

1 … 144
TBA






If you require a different
pad ring, then please contact
customer support.

silicon.pads#

The silicon.pads section lists special pads. In general you are unlikely to need to add to this.

For each pad, there’s a label which is used by our design, and what type and loc each pad should be.

type#

The type for each pad can be set to one of:

clock

External clock input.

i

Input.

o

Output.

io

Input or output.

loc#

This is the physical location of the pad on your chosen pad ring. How these are indexed varies by the pad ring.

silicon.power#

This section describes how the pads should be connected to the power available on the chosen process.

This is a work in progress, and currently you can use the defaults provided by customer support.