chipflow_lib.platforms

chipflow_lib.platforms#

Submodules#

Attributes#

PIN_ANNOTATION_SCHEMA

PACKAGE_DEFINITIONS

Classes#

SiliconPlatformPort

Represents an abstract library I/O port that can be passed to a buffer.

SiliconPlatform

SimPlatform

IOSignature

Amaranth Signtaure used to decorate wires that would

Functions#

OutputIOSignature(width, **kwargs)

InputIOSignature(width, **kwargs)

BidirIOSignature(width, **kwargs)

load_pinlock()

top_interfaces(config)

Package Contents#

class chipflow_lib.platforms.SiliconPlatformPort(component, name, port, *, invert=False)#

Bases: amaranth.lib.io.PortLike

Represents an abstract library I/O port that can be passed to a buffer.

The port types supported by most platforms are SingleEndedPort and DifferentialPort. Platforms may define additional port types where appropriate.

Note

amaranth.hdl.IOPort is not an instance of amaranth.lib.io.PortLike.

Parameters:

  • component (str)

  • name (str)

  • port (chipflow_lib.platforms.utils.Port)

  • invert (bool)

wire(m, interface)#
Parameters:
property i#
property o#
property oe#
property direction#

Direction of the port.

Return type:

Direction

property pins#
property invert#
class chipflow_lib.platforms.SiliconPlatform(config)#
property ports#
instantiate_ports(m)#
Parameters:

m (amaranth.Module)

request(name=None, **kwargs)#
get_io_buffer(buffer)#
add_file(filename, content)#
build(elaboratable, name='top')#
default_clock(platform, clock, reset)#
class chipflow_lib.platforms.SimPlatform#
build_dir#
extra_files#
clk#
rst#
buttons#
sim_boxes#
add_file(filename, content)#
add_model(inst_type, iface, edge_det=[])#
add_monitor(inst_type, iface)#
build(e)#
chipflow_lib.platforms.PIN_ANNOTATION_SCHEMA = ''#
class chipflow_lib.platforms.IOSignature(direction, width=1, all_have_oe=False, init=None)#

Bases: amaranth.lib.wiring.Signature

Amaranth Signtaure used to decorate wires that would usually be brought out onto a port on the package.

direction: Input, Output or Bidir width: width of port all_have_oe: For Bidir ports, should Output Enable be per wire or for the whole port init: a const-castable object for the initial values of the port

Parameters:
property direction#
width()#
options()#
annotations(*args)#

Annotate an interface object.

Subclasses of Signature may override this method to provide annotations for a corresponding interface object. The default implementation provides none.

See amaranth.lib.meta for details.

Returns:

tuple()

Return type:

iterable of Annotation

chipflow_lib.platforms.OutputIOSignature(width, **kwargs)#
chipflow_lib.platforms.InputIOSignature(width, **kwargs)#
chipflow_lib.platforms.BidirIOSignature(width, **kwargs)#
chipflow_lib.platforms.load_pinlock()#
chipflow_lib.platforms.PACKAGE_DEFINITIONS#
chipflow_lib.platforms.top_interfaces(config)#