chipflow_lib.steps.silicon

Attributes

logger

Classes

SiliconTop
SiliconStep	Prepare and submit the design for an ASIC.

Module Contents

chipflow_lib.steps.silicon.logger

class chipflow_lib.steps.silicon.SiliconTop(config={})

Bases: amaranth.Elaboratable

elaborate(platform)

Parameters:

platform (chipflow_lib.platforms.SiliconPlatform)

class chipflow_lib.steps.silicon.SiliconStep(config)

Prepare and submit the design for an ASIC.

config

config_model

project_name

silicon_config

platform

build_cli_parser(parser)

run_cli(args)

prepare()

Elaborate the design and convert it to RTLIL.

Returns the path to the RTLIL file.

submit(rtlil_path, *, dry_run=False, wait=False)

Submit the design to the ChipFlow cloud builder.