chipflow.sim.cxxrtl¶
CXXRTL C API bindings via ctypes.
This module provides Python bindings for the CXXRTL simulation engine, allowing fast compiled simulation of HDL designs with Python testbenches.
Classes¶
CXXRTL object descriptor - matches struct cxxrtl_object in cxxrtl_capi.h |
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Python wrapper for CXXRTL simulation. |
Module Contents¶
- class chipflow.sim.cxxrtl.CxxrtlObject¶
Bases:
ctypes.StructureCXXRTL object descriptor - matches struct cxxrtl_object in cxxrtl_capi.h
- class chipflow.sim.cxxrtl.CxxrtlSimulator(library_path, top_module)¶
Python wrapper for CXXRTL simulation.
This class provides a Pythonic interface to CXXRTL compiled simulations, supporting signal access, stepping, and VCD tracing.
Example:
sim = CxxrtlSimulator("build/design.so", "design") sim.reset() # Clock cycle sim.set("clk", 0) sim.step() sim.set("clk", 1) sim.step() # Read output value = sim.get("data_out")
- Parameters:
library_path (Union[str, pathlib.Path])
top_module (str)
- reset()¶
Reset the simulation to initial state.
- Return type:
None
- eval()¶
Evaluate combinatorial logic.
- Returns:
True if the design converged immediately
- Return type:
- step()¶
Simulate to a fixed point (eval + commit until stable).
- Returns:
Number of delta cycles
- Return type:
- get(name)¶
Get the current value of a signal.
- set(name, value)¶
Set the next value of a signal.
- signals()¶
Iterate over all signals in the design.
- Yields:
Tuples of (name, object) for each signal
- Return type:
Iterator[Tuple[str, CxxrtlObject]]
- inputs()¶
Iterate over input signals.
- Return type:
Iterator[Tuple[str, CxxrtlObject]]
- outputs()¶
Iterate over output signals.
- Return type:
Iterator[Tuple[str, CxxrtlObject]]
- close()¶
Release simulation resources.
- Return type:
None