chipflow.sim.build¶
Build CXXRTL shared libraries from HDL sources.
This module provides functions to compile Amaranth, Verilog, and SystemVerilog designs into CXXRTL shared libraries for fast simulation.
Functions¶
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Build a CXXRTL shared library from HDL sources. |
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Build CXXRTL from an Amaranth Elaboratable. |
Module Contents¶
- chipflow.sim.build.build_cxxrtl(sources, top_module, output_dir, output_name=None, include_dirs=None, defines=None, optimization='-O2', debug_info=True)¶
Build a CXXRTL shared library from HDL sources.
- Parameters:
sources (Sequence[Union[str, pathlib.Path]]) – List of Verilog/SystemVerilog source files
top_module (str) – Name of the top-level module
output_dir (Union[str, pathlib.Path]) – Directory for build artifacts
output_name (Optional[str]) – Name for output library (default: top_module)
include_dirs (Optional[Sequence[Union[str, pathlib.Path]]]) – Additional include directories for Verilog
defines (Optional[dict[str, str]]) – Verilog preprocessor defines
optimization (str) – C++ optimization level (default: -O2)
debug_info (bool) – Include CXXRTL debug info (default: True)
- Returns:
Path to the compiled shared library
- Return type:
- chipflow.sim.build.build_cxxrtl_from_amaranth(elaboratable, top_module, output_dir, amaranth_platform=None, extra_sources=None, **kwargs)¶
Build CXXRTL from an Amaranth Elaboratable.
This function generates Verilog from an Amaranth design and compiles it to a CXXRTL shared library, optionally combining with extra Verilog/SV sources.
- Parameters:
elaboratable – Amaranth Elaboratable to simulate
top_module (str) – Name for the top module
output_dir (Union[str, pathlib.Path]) – Directory for build artifacts
amaranth_platform – Amaranth platform (optional)
extra_sources (Optional[Sequence[Union[str, pathlib.Path]]]) – Additional Verilog/SV files to include
**kwargs – Additional arguments passed to build_cxxrtl()
- Returns:
Path to the compiled shared library
- Return type: