chipflow.packaging.standard

Standard package definitions for common package types.

This module provides concrete package definitions for: - Quad packages (QFN, LQFP, TQFP, etc.) - Bare die packages

Classes

BareDiePackageDef	Definition of a package with pins on four sides.
BlockPackageDef	Definition of a hard-macro target with pins on four sides.
QuadPackageDef	Definition of a quad flat package.

Module Contents

class chipflow.packaging.standard.BareDiePackageDef

Bases: chipflow.packaging.base.LinearAllocPackageDef

Definition of a package with pins on four sides.

Sides are labeled north, south, east, west with an integer identifier within each side, indicating pads across or down from top-left corner.

This is typically used for direct die attach without traditional packaging.

Attributes:

• width – Number of die pads on top and bottom sides

• height – Number of die pads on left and right sides

model_post_init(__context)

Initialize pin ordering

property bringup_pins: chipflow.packaging.pins.BringupPins

Bringup pins for bare die package

Return type:

chipflow.packaging.pins.BringupPins

class chipflow.packaging.standard.BlockPackageDef

Bases: chipflow.packaging.base.LinearAllocPackageDef

Definition of a hard-macro target with pins on four sides.

Structurally close to QuadPackageDef — pins are numbered linearly counter-clockwise starting from the top of the West edge — but used when the build is producing a block (LEF / Liberty / GDS for embedding into another design) rather than a packaged chip. Differences:

• No I/O pad ring, no JTAG, no power pins: blocks take power via straps from the parent and have no chip-level debug ring.

• The bringup pin set contains only core_clock (pin 1) and core_reset (pin 2). Clock and reset are real boundary signals on the macro that the parent design drives through ordinary block pins.

• width and height are pin-slot counts, same units as QuadPackageDef.width / .height — not microns. Translation to physical dimensions happens at the backend using the process’s pin pitch.

Linear pin numbering matches QuadPackageDef so the backend can use a single packaging.map convention to translate pin indices to physical (side, slot) locations.

Attributes:

• width – Number of pin slots on top and bottom edges.

• height – Number of pin slots on left and right edges.

model_post_init(__context)

Initialize pin ordering, subtracting the bringup slots.

property bringup_pins: chipflow.packaging.pins.BringupPins

clock at pin 1, reset at pin 2.

No power (parent abutment), no heartbeat, no JTAG. The base _allocate_bringup() walks the empty core_power list and skips heartbeat when core_heartbeat is None, so the resulting _core portmap contains just clk and rst_n.

Type:

Minimal bringup

Return type:

chipflow.packaging.pins.BringupPins

class chipflow.packaging.standard.QuadPackageDef

Bases: chipflow.packaging.base.LinearAllocPackageDef

Definition of a quad flat package.

A package with ‘width’ pins on the top and bottom and ‘height’ pins on the left and right. Pins are numbered anti-clockwise from the top left pin.

This includes many common package types:

• QFN: quad flat no-leads (bottom pad = substrate)

• BQFP: bumpered quad flat package

• BQFPH: bumpered quad flat package with heat spreader

• CQFP: ceramic quad flat package

• EQFP: plastic enhanced quad flat package

• FQFP: fine pitch quad flat package

• LQFP: low profile quad flat package

• MQFP: metric quad flat package

• NQFP: near chip-scale quad flat package

• SQFP: small quad flat package

• TQFP: thin quad flat package

• VQFP: very small quad flat package

• VTQFP: very thin quad flat package

• TDFN: thin dual flat no-lead package

• CERQUAD: low-cost CQFP

Attributes:

• width – The number of pins across on the top and bottom edges

• height – The number of pins high on the left and right edges

model_post_init(__context)

Initialize pin ordering

property bringup_pins: chipflow.packaging.pins.BringupPins

Bringup pins for quad package

Return type:

chipflow.packaging.pins.BringupPins