Wrapping External RTL

chipflow.rtl.wrapper turns a TOML description of an external Verilog or SystemVerilog module into an Amaranth Component ready to drop into a design. The TOML specifies the source files, clocks and resets, bus/pin interfaces, optional preprocessing (sv2v, yosys-slang, SpinalHDL), and — as of this release — Verilog module parameter overrides.

This page is an API-level pointer. For the full usage guide, worked examples, and the TOML reference, see the ChipFlow training material:

Quick reference

Load a wrapper from a TOML file and instantiate it inside a design:

from chipflow.rtl.wrapper import load_wrapper_from_toml

class MyDesign(wiring.Component):
    def elaborate(self, platform):
        m = Module()
        m.submodules.timer = load_wrapper_from_toml("wb_timer.toml")
        return m

Supply Verilog parameter overrides from TOML, from Python, or both (the Python kwarg wins on collisions; unmentioned parameters fall back to the TOML table):

# wb_timer.toml
name = "wb_timer"

[parameters]
DATA_WIDTH = 32
ADDR_WIDTH = 4

# caller overrides DATA_WIDTH; ADDR_WIDTH=4 still applies
w = load_wrapper_from_toml("wb_timer.toml", parameters={"DATA_WIDTH": 64})

The merged parameters are emitted as p_<NAME>=<value> kwargs on the Instance() at elaboration, and are also fed into generator template substitution (so SpinalHDL / sv2v / yosys-slang see the final values when producing Verilog).

API